Archive

The following is the regular meeting information for April.   

When: April 16, 2012 (Monday)     April 19 (Thursday)
Time: 6:00PM - 7:30PM 
Location: Freescale, Building B 
       7700 Parmer Ln 
       Austin, TX 78729 
(Enter the driveway to Freescale from Parmer Ln. See the details in the attachment) 



Agenda for the Meeting 

6:00PM to 6:30PM - Social with Food & Drinks 
6:30PM - Seminar starts 
      Technical presentation by Mr. Igor Alvarado 
      "The Role of Real-Time High-Performance Computing (RT-HPC) in the Evolution of the Advanced Manufacturing Industry" 
7:30PM - Meeting ends 
       Concluding Remarks 

Invited Speaker: Mr. Igor Alvarado, Academic Business Development Manager at National Instruments Corp.  

Topic:  The Role of Real-Time High-Performance Computing (RT-HPC) in the Evolution of the Advanced Manufacturing Industry 

Abstract:   
The Advanced Manufacturing Industry (e.g semiconductor) is rapidly evolving and requiring the use of computational tools in industrial settings for modeling, simulation, control and test. Real-time high-performance (embedded) computing (RT-HPC) tools in the form of software and hardware optimized for the integration of streaming data to/from sensors and actuators with online data analysis and visualization tasks are now an important component of advanced manufacturing systems in which numerical methods and mathematics are part of the control loop. Although the term HPC has been associated with offline simulations, RT-HPC is a new effort to bring HPC concepts and solutions to the manufacturing floor. For example, many of the new manufacturing devices and robots perform computationally intensive operations (performing one or more TFLOPS) and run complex algorithms and solvers in their embedded processors using the data captured with sensors and/or generated by simulations. In this technical presentation, we will show how a new hybrid, embedded architecture makes use of easy-to-use software tools, the latest multicore processors (CPUs), Field-programmable Gate Arrays (FPGAs) and Graphics Processing Units (GPUs) together with modular instruments (e.g. high-speed digitizers), data acquisition boards and programmable switches for developing the new generation of automated test equipment (ATE), controllers, analyzers and robotics-based devices that are required in today’s advanced manufacturing systems. 

Biography of Mr. Igor Alvarado: 
Mr. Alvarado is a Mechanical Engineer (Kansas State University, 1984) and currently works with National Instruments (NI) as an Academic Business Development Manager. He has been with NI for more than 13 years, and has more than 25 years practical experience in the design, development and deployment of real-time, distributed control systems (including Statistical Process Control-SPC and High-Availability Control Systems) that involve high-performance numerical methods in C, C++, FORTRAN and NI LabVIEW using PC-based and embedded technologies. He has also been involved in the design and implementation of novel approaches for teaching/learning science and engineering at the university level, with a special emphasis on hands-on learning and experimental research. He’s an active member of different professional and scientific associations among others, the Institute of Electrical and Electronics Engineers (IEEE), the Society of Industrial and Applied Mathematics (SIAM), the International Society of Automation (ISA), and the Ibero-American Science and Technology Education Consortium (ISTEC). Mr. Alvarado has taught courses to engineers and scientists involved in instrumentation, control and automation applications. He has been an invited speaker to a wide spectrum of scientific and technical conferences and meetings. 

Upcoming future events: 
May 17, 2012 - 3D TSV Challenges and Opportunities, Dr. Jan Vardaman, Tech Search Inc. 
Recess in June, 2012 
Regular technical meetings will resume in August 

IEEE CPMT Austin Chapter will host a seminar by Dr. Jay Im on "Experimental Methods and FEA for Reliability Assessment of 3D TSV Structures" on March 15, 2012 (Thur) as part of monthly seminar series inviting local industry experts. 

Please join us in networking with technical community colleagues and learning from each other in our local technical community. Also a job opening information for signal integrity engineers is available at the end of this email for anyone who may be interested. 
  
When: March 15, 2012 (Thursday) 
Time: 6:00PM - 7:30PM 
Location: Freescale, Building B 
          7700 Parmer Ln 
          Austin, TX 78729 
(Enter the driveway to Freescale from Parmer Ln. See the details in the attachment) 


Agenda for the Meeting 

6:00PM to 6:30PM - Social with Food & Drinks 
6:30PM - Seminar starts 
         Technical presentation by Dr. Jay Im 
         "Experimental Methods and FEA for Reliability Assessment of 3D TSV Structures" 
7:30PM - Meeting ends 
          Concluding Remarks 

Invited Speaker: Dr. Jay Im, UT at Austin 

Topic:  Experimental Methods and FEA for Reliability Assessment of 3D TSV Structures 

Abstract:  

Various experimental techniques were employed on the TSV samples containing periodic arrays of blind Cu vias in silicon. With a precision optical system, the curvature variations of the specimens under repeated thermal cycles were monitored. With electron backscattering diffraction (EBSD) and focused ion beam (FIB) techniques, Cu grain growth with temperature history was investigated. With Raman spectroscopy, the (sum of) near surface stresses surrounding the TSVs were obtained.   
The curvature behaviors were distinctly different from pristine Cu thin films due to triaxiality of stresses in the Cu vias. The reverse pole figure in EBSD, together with linearity of curvature in thermal cycles between fixed temperatures, demonstrated an isotropic nature of Cu grain orientation in the vias. This finding enabled adopting linear elastic assumption for detailed stress computation using finite element analysis (FEA) in the Cu vias as well as in the Si matrix. In the latter case of Si matrix, the FEA results agreed reasonably well with the Raman. Therefore, from the FEA stresses, the carrier mobility changes were calculated and the keep-out zone (KOZ) determined. 

Biography of Dr. Jay Im: 
For the past 7 years, Jay Im has been a Research Professor, working at Prof. Paul Ho’s Laboratory for Interconnect & Packaging at The University of Texas at Austin. His research areas at the University are in semiconductor packaging and reliability, 3D integration with TSVs, electromigration of Pb-free solders, materials science of dielectric films, and metrology for thin film testing.  Prior to UT, he had been with The Dow Chemical Company for over 28 years, taking on various R&D positions including Research Scientist in Microelectronics, where he headed the materials science and adhesion efforts for BCB and SiLK dielectric polymers.  He received his BS degree in mechanical engineering from Seoul National University, and both MS degree in mechanical engineering and Sc.D degree in materials science & engineering from Massachusetts Institute of Technology.  He has approximately 120 published papers and 9 US patents.  He is a Senior Member of IEEE.

IEEE CPMT Austin Chapter will host a seminar by Dr. Brian Young on "Causality, Causality Checking, and Impact on Time-Domain Simulation" on February 16, 2011 (Thur) as part of monthly seminar series inviting local industry experts. 

Please join us in networking with technical community colleagues and learning from each other in our local technical community. Also a job opening information for signal integrity engineers is available at the end of this email for anyone who may be interested. 
  
When: February 16, 2012 (Thursday) 
Time: 6:00PM - 7:30PM 
Location: Freescale, Building B 
          7700 Parmer Ln 
          Austin, TX 78729 
(Enter the driveway to Freescale from Parmer Ln. See the details in the attachment) 


Agenda for the Meeting 

6:00PM to 6:15PM - Social with Food & Drinks 
6:15PM to 6:35PM - IEEE membership benefits and membership upgrade event 
6:35PM - Seminar starts 
         Technical presentation by Dr. Brian Young 
         "Causality, Causality Checking, and Impact on Time-Domain Simulation" 
7:30PM - Meeting ends 
          Concluding Remarks 

Invited Speaker: Dr. Brian Young, Texas Instruments (TI) 

Topic:  Causality, Causality Checking, and Impact on Time-Domain Simulation 

Abstract:   
Models computed in the frequency domain are frequently used in time-domain simulations to capture complex electromagnetic phenomena such as time retardation, skin effect losses, and current crowding effects.  There are a large number of variables that must be correctly set to produce a good model, but how is the modeler to know that everything is right and that the model is usable?  For time-domain simulations, the model must produce a causal result, so a necessary condition for the model to be good is that it is causal.  A causality checker can be used as a very strong quality control check to ensure that models produced from frequency-domain data are good.  The presentation briefly derives the Hilbert Transform and a causality checker based on it, then proceeds to a very practical set of real-world demonstrations of the utility of causality checkers for quality control and for basing extraction setup parameters such as frequency spacing and extraction bandwidth. 

Biography of Dr. Brian Young: 
Dr. Brian Young received the BSEE from Texas A&M University in 1984, the MSEE from the University of Illinois in 1985, and the PhD from the University of Texas in 1987.  He taught electromagnetics and microwaves at Texas A&M University before moving to Hughes Aircraft to design microwave circuits and packaging for transmit/receive modules for phased array radar.  He then transitioned to Motorola to develop modeling, simulation and characterization techniques for digital packaging.  This was followed by LVCMOS, LVDS, and HSTL IO circuit design at Motorola and Texas Instruments.  In 2005, he started a new signal and power integrity group at Texas Instruments to ensure the successful integration of high-performance ASICs, and he now also manages the package design team in the ASIC product group.  He was an Associate Editor for the IEEE Transactions on Advanced Packaging from 2001 to 2003.  He is on the technical program committee for the IEEE Conference on Electrical Performance of Electronic Packaging and Systems, and he is the conference co-chair for 2011-2012.  He is the author of the book “Digital Signal Integrity: Modeling and Simulation with Interconnects and Packages” and has authored or co-authored 33 papers and conference publications, and he holds 8 patents.  He is a registered professional engineer in the state of Texas. 


IEEE CPMT Austin Chapter will host a seminar by Dr. Dipanjan Gope on "3D Full-wave, Package-Board Simulation Aided by the Cloud" on November 17, 2011 (Thur) as part of monthly seminar series inviting local industry experts. 

Please join us in networking with technical community colleagues and learning from each other in our local technical community. Also a job opening information for signal integrity engineers is available at the end of this email for anyone who may be interested. 
  
When: November 17, 2011 (Thursday) 
Time: 6:00PM - 7:30PM 
Location: Freescale, Building B 
7700 Parmer Ln 
Austin, TX 78729 
(Enter the driveway to Freescale from Parmer Ln. See the details in the attachment) 

Agenda for the Meeting 

6:00PM to 6:20PM - Social with Food & Drinks 
6:20PM - Meeting Starts 
Welcome of the guests and Speaker Introduction
6:30PM - Seminar starts 
Technical presentation by Dr. Dipanjan Gope 
"3D Full-wave, Package-Board Simulation Aided by the Cloud" 
7:30PM - Meeting ends 
Concluding Remarks 

Invited Speaker: Dr. Dipanjan Gope, Nimbic 

Topic:  3D Full-wave, Package-Board Simulation Aided by the Cloud 

Abstract:  

The drive towards high-performance, high-functionality, low-cost packages has given rise to an increased requirement for using 3D full-wave electromagnetic solvers for design and verification. However, analysis of large scale package-board systems present significant challenges in terms of memory capacity to fit the solver matrix, and time-bottlenecks preventing quick turnaround required for early design optimization. Fast solver algorithms developed over the last 2 decades have alleviated the problems to an extent. The emergence of cloud computing and the corresponding on-demand availability of custom computing instances, presents a unique opportunity to meet the time-memory requirements and enter the “simulation-in-a-coffee-break” paradigm. In order to harness the true potential of the cloud infrastructure, a multilevel parallelization scheme is adopted: 
(a)    The bottom-most parallelization layer consists of multi-threading with OpenMP to utilize the many cores of an individual machine instance and the available shared memory. 
(b)   The second layer uses Message Passing Interface (MPI) to seamlessly combine the shared-memory on multiple instances to fit a larger matrix size. 
(c)    The third layer uses SGE to distribute the multiple port solutions in the solve stage. 
(d)   The top-most layer is an umbrella of SGE that parallelizes for discrete frequency or parametric sweeps, a type of parallelization which fall under the so-called “pleasingly parallel” form.

Biography of Dr. Dipanjan Gope: 
Dr. Dipanjan Gope (M’05), PhD, is Vice President of R&D at Nimbic. His research interests include fast solver engines for circuit-electromagnetic simulation, parallelization algorithms and cloud computing. Prior to joining Nimbic (previously Physware), he was a Senior CAD engineer at Intel and a technical research intern at T.J. Watson IBM Research Center. Dr. Gope is a recipient of CTC divisional award at Intel for contributions to on-chip signal integrity analysis. He co-developed the PILOT technology for fast circuit-electromagnetic simulation, now licensed by the University of Washington. He has over 40 journal and conference publications. Dr. Gope received his PhD and M.S. degrees in EE from the University of Washington, Seattle and BTech in Electronics and Electrical Communication from the Indian Institute of Technology, Kharagpur.

Upcoming future seminar series: 
Feb. 15, 2012 - Causality, Checking causality, and Impact on time-domain simulations, Dr. Brian Young, TI 
Mar. 19, 2012 - Stress issues on Cu-TSV performance and investigating grain structure changes by thermal cycle test, Dr. Jay Im, UT 

For more information, please visit http://cpmtaustinchapter.org/Tips.html 

Job Opening in Molex - SI engineer: The SI engineer position can be based in Lisle, IL(preferred) or Austin, TX. The requirements are: solid understanding transmission line and EM theories; experiences with high-speed channel modeling and simulation; hands on experiences with VNA/TDR testings; proficient with HFSS or equivalent high frequency simulation; 
The job responsibilities include but not limited to: connector designs and modeling, channel modeling, customer’s design support etc.  If interested, please send resume to xin.wu@molex.com . 

Seminar by Rekha Bangalore on "Thermal management for Solid State Lighting" on October 20, 2011 (Thur) as part of monthly seminar series inviting local industry experts. 

When: October 20, 2011 (Thursday) 
Time: 6:00PM - 7:30PM 
Location: Freescale, Building B 
7700 Parmer Ln 
Austin, TX 78729 
(Enter the driveway to Freescale from Parmer Ln. See the details in the attachment) 


Agenda for the Meeting 

6:00PM to 6:20PM - Social with Food & Drinks 
6:20PM - Meeting Starts 
Welcome of the guests and Speaker Introduction
6:30PM - Seminar starts 
Technical presentation by Rekha Bangalore 
"Thermal Management of Solid State Lighting" 
7:30PM - Meeting ends 
Concluding Remarks 

Invited Speaker: Rekha Bangalore 

Topic: Thermal Management for Solid State Lighting 

Abstract: Light Emitting Diodes (LED) are expected to replace the incandescent and compact fluorescent lighting in the next few years. LED’s consume less power thereby saving more energy and also provides an environmentally sustainable technology. According to Department of Energy, it is estimated that switching to LED lighting over the next two decades could save the country $120 billion in energy costs, reduce the electricity consumption for lighting by one-fourth, and avoid 246 million metric tons of carbon emission. However, there are some barriers for deployment and this is due to the   efficiency of LED measured by Lumens per Watt and is impacted by two technological challenges; Driver Efficiency (Efficiency in Integrated circuits which provides a stable power to the LED) and Thermal Management (Efficiency of LED impacted by the junction temperature of LED.  Heating impacts the CCT and performance of LED). The techniques used to solve the efficiency are discussed in the presentation. These include development of innovative driver integrated circuits for LED’s and new types of thermal interface materials for reducing the LED junction temperature.

Biography of Rekha Bangalore: 
Rekha Bangalore has been in the semiconductor industry for eighteen years and she has worked with Intel, Motorola and Freescale. At Freescale, she was named Distinguished Member of Technical Staff/Design Manager. Her experience is in technology innovation in semiconductor, design innovations and renewable energy. Rekha Bangalore is the founder of Ix-Neox, a high tech start-up in Austin, Texas.  She deeply understands technology and developing high tech products. She has experience working with national labs, negotiating licenses and implementing technology evaluations and business plans and has applied for patents in solar lighting and nano-technology thermal management. Her current role as adjunct faculty in ACC(Austin Community College) enables her to teach digital electronics and FPGA course for technology deployment.  Rekha Bangalore holds Bachelor of Science and Master of Science degrees in Electronics and Computer Engineering, and a Master of Science in Technology Commercialization from the University of Texas at Austin. Education and teaching have always been core passions in her life.  Her industry experience enables her to uniquely combine technology, education and methodology that is highly beneficial to her students learning.

Upcoming future seminar series: 
Nov. 17, 2011 - 3D Full-wave, Package-Board Simulation Aided by the Cloud by Dr. Dipanjan Gope 
Feb. 15, 2012 - 3D-TSVs overview and status by Thuy Dao 

For more information, please visit http://cpmtaustinchapter.org/Tips.html

September 15, 2011    
    3D Technology Evolution From Components to Systems    Dr. Michael Shapiro    IBM

3D Technology Evolution From Components to Systems